Crate prjunnamed_netlist

This library provides the in-memory form of the Project Unnamed IR.

A Design is represented as a sea of Cells identified by a contiguous range of indices, connected by Nets and Values that refer back to cells by their index. This representation is equally suited for bit-level and word-level netlists, including bit-level cells with multiple outputs.

Macros

• assert_isomorphic

Structs

• AssignCell
  If enable is asserted, output is value where value[offset..] is replaced with update. Otherwise it is value.
• CellRef
• Const
  A constant is a (possibly empty) sequence of Trits.
• Design
  Sea of Cells.
• FlipFlop
  A flip-flop cell.
• Instance
• IoBuffer
• IoNet
• IoValue
• MatchCell
  If enable is asserted, output is one-hot priority match of value against patterns. Otherwise it is zero.
• Memory
  An all-in-one random-access memory cell.
• MemoryReadFlipFlop
  A structure describing a synchronous read port’s control signals and behavior.
• MemoryReadPort
  A memory read port, either synchronous or asynchronous.
• MemoryWritePort
  A synchronous memory write port.
• MetaItemRef
• MetaStringRef
• Net
  A net is a driver in the design; either a constant (a Trit) or a reference to a single position from the output of a Cell.
• ParseError
• SourcePosition
  Position within a source file.
• TargetCell
• TargetImportError
• TargetInput
• TargetIo
• TargetOutput
• TargetParam
• TargetPrototype
• Value
  A value is a (possibly empty) sequence of Nets.
• WithMetadataGuard

Enums

• Cell
  A unit of logic.
• ControlNet
  A control net is a Net that can be negated.
• MemoryPortRelation
• MetaItem
  Metadata item.
• NotIsomorphic
• ParamValue
• SmtResponse
• TargetCellImportError
• TargetCellPurity
• TargetParamKind
• Trit
  An extended binary value.

Traits

• SmtEngine
• Target

Functions

• create_target
• isomorphic
• parse
• register_target