Expand description
This library provides the in-memory form of the Project Unnamed IR.
A Design
is represented as a sea of Cell
s identified by a contiguous range of indices,
connected by Net
s and Value
s that refer back to cells by their index. This representation
is equally suited for bit-level and word-level netlists, including bit-level cells with multiple
outputs.
Macros§
Structs§
- If
enable
is asserted, output isvalue
wherevalue[offset..]
is replaced withupdate
. Otherwise it isvalue
. - A constant is a (possibly empty) sequence of
Trit
s. - Sea of
Cell
s. - A flip-flop cell.
- If
enable
is asserted, output is one-hot priority match ofvalue
againstpatterns
. Otherwise it is zero. - An all-in-one random-access memory cell.
- A structure describing a synchronous read port’s control signals and behavior.
- A memory read port, either synchronous or asynchronous.
- A synchronous memory write port.
- Position within a source file.
- A value is a (possibly empty) sequence of
Net
s.
Enums§
- A unit of logic.
- A control net is a
Net
that can be negated. - Metadata item.
- An extended binary value.