Expand description
This library provides the in-memory form of the Project Unnamed IR.
A Design is represented as a sea of Cells identified by a contiguous range of indices,
connected by Nets and Values that refer back to cells by their index. This representation
is equally suited for bit-level and word-level netlists, including bit-level cells with multiple
outputs.
Macros§
Structs§
- Assign
Cell - If
enableis asserted, output isvaluewherevalue[offset..]is replaced withupdate. Otherwise it isvalue. - CellRef
- Const
- A constant is a (possibly empty) sequence of
Trits. - Design
- Sea of
Cells. - Flip
Flop - A flip-flop cell.
- Instance
- IoBuffer
- IoNet
- IoValue
- Match
Cell - If
enableis asserted, output is one-hot priority match ofvalueagainstpatterns. Otherwise it is zero. - Memory
- An all-in-one random-access memory cell.
- Memory
Read Flip Flop - A structure describing a synchronous read port’s control signals and behavior.
- Memory
Read Port - A memory read port, either synchronous or asynchronous.
- Memory
Write Port - A synchronous memory write port.
- Meta
Item Ref - Meta
String Ref - Net
- A net is a driver in the design; either a constant (a
Trit) or a reference to a single position from the output of aCell. - Parse
Error - Source
Position - Position within a source file.
- Target
Cell - Target
Import Error - Target
Input - Target
Io - Target
Output - Target
Param - Target
Prototype - Value
- A value is a (possibly empty) sequence of
Nets. - With
Metadata Guard
Enums§
- Cell
- A unit of logic.
- Control
Net - A control net is a
Netthat can be negated. - Memory
Port Relation - Meta
Item - Metadata item.
- NotIsomorphic
- Param
Value - SmtResponse
- Target
Cell Import Error - Target
Cell Purity - Target
Param Kind - Trit
- An extended binary value.