Enum Cell

pub enum Cell {
    Buf(Value),
    Not(Value),
    And(Value, Value),
    Or(Value, Value),
    Xor(Value, Value),
    Mux(Net, Value, Value),
    Adc(Value, Value, Net),
    Eq(Value, Value),
    ULt(Value, Value),
    SLt(Value, Value),
    Shl(Value, Value, u32),
    UShr(Value, Value, u32),
    SShr(Value, Value, u32),
    XShr(Value, Value, u32),
    Mul(Value, Value),
    UDiv(Value, Value),
    UMod(Value, Value),
    SDivTrunc(Value, Value),
    SDivFloor(Value, Value),
    SModTrunc(Value, Value),
    SModFloor(Value, Value),
    Match(MatchCell),
    Assign(AssignCell),
    Dff(FlipFlop),
    Memory(Memory),
    IoBuf(IoBuffer),
    Target(TargetCell),
    Other(Instance),
    Input(String, usize),
    Output(String, Value),
    Name(String, Value),
    Debug(String, Value),
}

A unit of logic.

Within a Design, each cell is identified by a range of indices, with each index corresponding to one of the output bits of the cell. As such, the cell itself only contains information about its inputs, with the outputs being implicit.

(do note that cells without any outputs, such as output or name, still get assigned an index)

Variants

Buf(Value)

Not(Value)

And(Value, Value)

a & b.

Has short-circuiting behavior for inputs containing X — if the other bit is 0, the output is 0 and the X doesn’t propagate.

Or(Value, Value)

a | b.

Has short-circuiting behavior for inputs containing X — if the other bit is 1, the output is 1 and the X doesn’t propagate.

Xor(Value, Value)

Mux(Net, Value, Value)

a ? b : c.

Muxes are glitch free — if a is X, the bit positions that match between b and c still have a defined value. The X propagates only at the positions where b and c differ.

Adc(Value, Value, Net)

a + b + ci — add with carry.

Output is one bit wider than a and b — the most significant bit is the carry-out.

Xs in the input propagate only to the more significant bits, and do not affect the less significant bits.

Eq(Value, Value)

ULt(Value, Value)

SLt(Value, Value)

Shl(Value, Value, u32)

a << (b * c). The bottom bits are filled with zeros.

General notes for all shift cells:

• output is the same width as a. If you need wider output, zero-extend or sign-extend your input first, as appropriate.
• the shift count does not wrap. If you shift by more than a.len() - 1, you get the same result as if you made an equivalent sequence of 1-bit shifts (i.e. all zeros, all sign bits, or all X, as appropriate).
• shift cells are one of the few cells which do not expect their inputs to be of the same width. In fact, that is the expected case.

UShr(Value, Value, u32)

a >> (b * c). The top bits are filled with zeros.

See also general notes above.

SShr(Value, Value, u32)

a >> (b * c). The top bits are filled with copies of the top bit of the input.

a must be at least one bit wide (as otherwise there would be no sign bit to propagate, and while there wouldn’t be anywhere to propagate it to, it’s an edge-case it doesn’t make sense to bother handling).

See also general notes above.

XShr(Value, Value, u32)

a >> (b * c). The top bits are filled with X.

See also general notes above.

Mul(Value, Value)

UDiv(Value, Value)

UMod(Value, Value)

SDivTrunc(Value, Value)

SDivFloor(Value, Value)

SModTrunc(Value, Value)

SModFloor(Value, Value)

Match(MatchCell)

Assign(AssignCell)

Dff(FlipFlop)

Memory(Memory)

IoBuf(IoBuffer)

Target(TargetCell)

Other(Instance)

Input(String, usize)

Design input of a given width.

If synthesizing for a specified target, and not in out-of-context mode, an input will be replaced with an IoBuffer and attached to a pin on the target device.

Output(String, Value)

Design output. Attaches a name to a given value.

If synthesizing for a specified target, and not in out-of-context mode, an output will be replaced with an IoBuffer and attached to a pin on the target device.

Name(String, Value)

Attaches a name to a given value for debugging.

Name keeps a given value alive during optimization and makes it easily available to be poked at during simulation.

Do note that the unname pass, which runs during target-dependent synthesis, replaces all Name cells with Debug cells.

Debug(String, Value)

Tentatively attaches a name to a given value.

Debug gives a name to a particular value, without insisting on keeping it alive during optimization. This helps correlate the output of synthesis with the corresponding input logic.

If at any point a value is being kept alive only by a Debug cell, it will be optimized out and the input to the Debug cell will be replaced with X.

See also: Name.

Implementations

impl Cell

pub fn validate(&self, design: &Design)

pub fn slice(&self, range: impl RangeBounds<usize> + Clone) -> Option<Cell>

If possible, return a cell that computes only a slice of the outputs of this cell.

impl Cell

pub fn output_len(&self) -> usize

pub fn has_effects(&self, design: &Design) -> bool

pub fn visit(&self, f: impl FnMut(Net))

pub fn visit_mut(&mut self, f: impl FnMut(&mut Net))

Trait Implementations

impl Clone for Cell

fn clone(&self) -> Cell

Returns a copy of the value.

fn clone_from(&mut self, source: &Self)

Performs copy-assignment from source.

impl Debug for Cell

fn fmt(&self, f: &mut Formatter<'_>) -> Result

Formats the value using the given formatter.

impl<'a> From<&'a Cell> for Cow<'a, Cell>

fn from(value: &'a Cell) -> Self

Converts to this type from the input type.

impl From<Cell> for Cow<'_, Cell>

fn from(value: Cell) -> Self

Converts to this type from the input type.

impl Hash for Cell

fn hash<__H: Hasher>(&self, state: &mut __H)

Feeds this value into the given Hasher.

fn hash_slice<H>(data: &[Self], state: &mut H)

where H: Hasher, Self: Sized,

Feeds a slice of this type into the given Hasher.

impl PartialEq for Cell

fn eq(&self, other: &Cell) -> bool

Tests for self and other values to be equal, and is used by ==.

fn ne(&self, other: &Rhs) -> bool

Tests for !=. The default implementation is almost always sufficient, and should not be overridden without very good reason.

impl Eq for Cell

impl StructuralPartialEq for Cell